As the semiconductor industry introduces new generations of integrated circuits (IC's) having higher performance and greater functionality, the density of the elements that form the integrated circuits is increased, and the dimensions, sizes and spacing between the individual components or elements are reduced. While in the past such reductions were limited only by the ability to define the structures photo-lithographically, device geometries having even smaller dimensions created new limiting factors. For example, for any two adjacent conductive paths, as the distance between the conductors decreases, the resulting capacitance (a function of the dielectric constant (k) of the insulating material divided by the distance between conductive paths) increases. This increased capacitance results in increased capacitive coupling between the conductors, increased power consumption, and an increase in the resistive-capacitive (RC) time constant. Therefore, continual improvement in semiconductor IC performance and functionality is dependent upon developing materials that form a dielectric film with a lower dielectric constant (k) than that of the most commonly used material, silicon oxide, in order to reduce capacitance. As the dimensions of these devices get smaller and smaller, significant reduction in capacitance into the so-called “ultra low-k” regime is required.
New materials with low dielectric constants (known in the art as “low-k dielectrics”) are being investigated for use as insulators in semiconductor chip designs. A low dielectric constant material aids in enabling further reduction in the integrated circuit feature dimensions. In conventional IC processing, SiO2 is used as a basis for the dielectric material, resulting in a dielectric constant of about 3.9. Moreover, advanced low-k dielectric materials have dielectric constants below about 2.7. The substance with the lowest dielectric constant is air (k=1.0). Therefore, porous dielectrics are very promising candidates since they have the potential to provide very low dielectric constants.
However, porous films are mechanically weak by nature. Weak films fail during the chemical mechanical polish (CMP) process employed to planarize the wafer surface during chip manufacturing. The mechanical properties of a porous film are functions of the porosity of the film. Naturally, higher porosity results in a lower dielectric constant but also poorer mechanical properties. Typically, cracking and/or peeling often occur during subsequent processing and/or packaging steps.
As is known in the art, one of the causes of cracking and peeling is poor adhesion between the low-k dielectric layers and underlying/overlying layers. Due to the poor adhesion problem, the usage of low-k dielectrics is limited, and thus a method that maximizes the benefit of low-k dielectrics while reducing the effects of weak mechanical properties is needed.